1. Field of the Invention
The present invention relates to a circuit and more particularly to an enhanced debug circuit for (Logic Built-In Self Test) LBIST testing.
2. Description of the Related Art
LBIST has been extensively used within IBM for testing of faults in chips. Published materials about LBIST include E. B. Eichelbergr and E. Lindbloom, “Random-Pattern Coverage Enhancement and Disgnosis for LSSD Logic Self-Test,” IBM J. Research and Development, Vol. 27, No. 3, May 1983, pp. 265-272; T. W. Williams and E. B. Eichelberger, “Random Patterns Within a Structured Sequential Logic Design,” Digest of Papers 1977 Semiconductor Test Symp, IEEE, October 1977, pp. 19-26; P. Bardell and W. McAnney, “Self-Testing of Multichip Logic Modules,” Digest of Papers 1982, pp. 200-204; D. Komonytsky, “LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis,” Degest of Papers 1982 Int'l Test Conf. IEEE, November 1982, pp. 414-424; E. B. Eichelberger and T. Williams, “A logic Design Structure for LSI Testability,” J. Design Automation and Fault Tolerant Computing, Vol. 2, No. 2, May 1978, pp. 165-178; and F. Motika, et al., “An LSSD Pseudo Random Pattern Test System,” Int'l TestConf. 1983 Proc. IEEE., October 1983, pp. 283-288. The above-mentioned publications are incorporated herein by reference.
To try to ensure that microprocessor chips have no hidden defects, chips are tested using LBIST, whereby all the logic on the microprocessor chip is tested using a large number of patterns to ensure a high test coverage. Typically, after each pattern, the resultant data in each “string” of latches are combined to form one “signature” which depends on values of all the individual latch bits. This signature is updated after each test, so that in the end, the final signature depends on the values of all the latch bits, as determined after all tests. The correct signature can be determined by simply running the tests at low frequency, where everything is sure to pass the test. The test signature generated from this low frequency testing will be referred as “the golden signature.” This golden signature is then used to compare against signatures obtained as the test frequency is increased. In this way, tens, or hundreds of thousands (or millions) of patterns can be used in the tests, since there is only one compare step, at the end of the process, and the business of calculating the signatures is done on the fly, as each test is completed. Although the chip will usually be divided up into many scan “strings,” each of which has its own signature, and each of which can be tested separately, it can be seen that, in any given string, as soon as a single latch fails, the signature will be altered.
Since the signature doesn't include any detailed information about which latch failed during which pattern, further debugging beyond this point becomes very difficult. For example, given the knowledge that latch “A” fails first as the testing frequency is ramped up, it would be very useful to be able to find out at what frequency the next failure occurs (say latch “B” in the same string). However, as soon as latch “A” starts failing, the signature no longer matches the golden signature, and, as the test frequency is raised, there is no way to identify when other latches start to fail. There is no way to determine a new “golden” signature which accounts for the failure in latch “A,” since the failure may occur on many of the test patterns, and as the frequency is changed, the number of “failures” changes in an unpredictable way, meaning that the signature changes unpredictably as well. This is a source of the problem for fault testing in LBIST.
Hence, it is desirable to provide an enhanced debug circuit which can provide a method and apparatus for screening out failures and obtaining a new signature, such that the test can be continued to higher frequencies.